1. Field of the Invention
The present invention relates to a semiconductor memory such as a DRAM (Dynamic Random Access Memory), and, more particularly, to a semiconductor memory suitable for a memory module complying with the FB-DIMM (Fully-Buffered Dual In-line Memory Module) standard.
Priority is claimed on Japanese Patent Application No. 2006-278470 filed on Oct. 12, 2006, the content of which is hereby incorporated by reference.
2. Description of Related Art
With the development of fine processing technology, an attempt has been diligently made to enlarge the capacity of a semiconductor memory typified by a DRAM. Generally, in order to improve the yield of products, the semiconductor memory has a redundant circuit including spare rows (redundant rows) and spare columns (redundant columns) used for defect relief (i.e., used for aid to defects). Addresses to be replaced by the spare rows and the spare columns are programmed into a fuse circuit.
This type of semiconductor memory includes a roll-call function to determine whether a redundant circuit is being used and a verify function to verify whether addresses for defect relief have been correctly set in the fuse circuit, both of which serve as functions in a test mode. The use of the test mode makes it possible to easily verify the operation of the redundant circuit. Verification results obtained in the test mode are output to an outer device through a data terminal (DQ terminal).
A memory module complying with the R-DIMM (Registered DIMM) standard or the U-DIMM (Unregistered DIMM) standard is known as a memory module composed of a plurality of semiconductor memories. The whole structure of a memory module 7 complying with the R-DIMM standard is shown in FIG. 8A. In this figure, reference symbol 7A designates a semiconductor memory (DRAM), reference symbol 7B designates a register, and reference symbol 7C designates an electrode of the memory module 7. In this example, six semiconductor memories 7A are mounted on the memory module 7. As is understood from FIG. 5B, input signal terminals of the semiconductor memory 7A are connected to the electrode 7C through the register 7B, whereas output signal terminals of the semiconductor memory 7A are connected directly to the electrode 7C without passing through the register 7B.
This R-DIMM standard employs a stub type as a mode for the connection of a channel signal line (i.e., an external signal line connected to the electrode 7C of the memory module 7). Therefore, if the number of memory modules per channel is increased, a capacity associated with the channel signal line is enlarged, and, in addition, noise on the channel signal line is enlarged. Therefore, a high-speed type semiconductor memory having only a slight timing margin has a problem in the fact that a delay and deterioration in a channel signal are caused. As a result, the number of memory modules per channel is restricted, and, disadvantageously, this restriction causes a bottleneck in improving the performance of a server system that needs high-speed and high-capacity semiconductor memories. The same problem arises in a semiconductor memory complying with the U-DIMM standard.
Consequently, in recent years, correspondingly to an increase in data transfer rate of a system and an increase in capacity thereof, the FB-DIMM standard has been promoted by JEDEC (Joint Electron Device Engineering Council) so as to serve as a new standard according to which the problems mentioned above are overcome. A high-speed memory module complying with this FB-DIMM standard has been proposed.
FIG. 9A shows the whole structure of a memory module 8 complying with the FB-DIMM standard. In this figure, reference symbol 8A designates a semiconductor memory (DRAM), reference symbol 8B designates a buffer called “AMB” (Advanced Memory Buffer), and reference numeral 8C designates an electrode of the memory module 8. In this example, six semiconductor memories 8A are mounted on the memory module 8. As is understood from FIG. 9B, all signal terminals of the semiconductor memory 8A are connected to the electrode 8C through the buffer 8B. Thus, the timing margin of the semiconductor memory 8A is secured by buffering all signals by use of the buffer 8B.
Additionally, the FB-DIMM standard employs a point-to-point connection method (serial connection method) as a mode for the connection of the channel signal line. Therefore, even if the number of memory modules per channel is increased, the capacity of the channel signal line through which modules are connected together comes to a fixed amount, and noise on the channel signal line is restrained. As a result, a delay and deterioration in a channel signal are improved, thus making it possible to fully utilize the characteristics of a high-speed type semiconductor memory having only a slight timing margin and to allow the semiconductor memory to perform an ultrahigh-speed operation.
However, a problem with a conventional semiconductor memory is that the roll-call function and the verify function cannot be used if the conventional semiconductor memory is incorporated into a memory module complying with the FB-DIMM standard.
In more detail, when data is output in an ordinary read mode, a semiconductor memory developed in recent years outputs a data strobe signal together with the data. On the system side, the output timing of the data is determined by referring to the data strobe signal, so that this data can be exactly obtained. When the thus structured semiconductor memory is incorporated into a memory module of the FB-DIMM standard, all signals including the data are targeted to be buffered by the AMB mentioned above. Therefore, when data is output, the semiconductor memory is required to simultaneously output a data strobe signal regardless of the operation mode.
However, the conventional semiconductor memory cannot output a data strobe signal in a test mode. In more detail, when a command that starts the verify function is given to a semiconductor memory as a test mode at time t10 as shown in FIG. 10, its verification result is output from the semiconductor memory as data DQ at time t20. However, a data strobe signal DQS is not output, and a high-impedance state is maintained. Therefore, the data DQ is not buffered in the AMB of the memory module, so that the data DQ cannot be output from the memory module.
Therefore, even if the test mode (e.g., the roll-call function, verify function) is started, its verification result cannot be output from the memory module. After all, the circuit operation of the semiconductor memory cannot be verified by the test mode.